(1) Field of the Invention
The invention relates to memory controllers. More specifically, the invention relates to memory controllers having a mid-transaction refresh capability and the ability to handle a master not ready signal.
(2) Prior Art
Accessing dynamic random access memory (DRAM) is generally well known in the art. In a typical DRAM access a memory controller receives an address from a master seeking the access. The address is decoded and mapped to form a row address and a column address. The memory controller then asserts a row address strobe (RAS) and the row address is strobed into the DRAM from the memory address (MA) lines of the DRAM. After the row address has been received, while maintaining RAS asserted, the column address is strobed into the DRAM from the MA lines by the assertion of a column address strobe (CAS). Each assertion of CAS corresponds to one transfer. If the transfer is a read, the data corresponding to the specified address is driven onto the data lines after CAS is asserted, and the master reads the data some time after it becomes valid. If the transaction is a write, data is written to the specified address on the falling edge of CAS.
Multiple accesses can be performed within one transaction. This is referred to as bursting. In a burst transaction RAS is maintained asserted and CAS is repeatedly asserted and deasserted equal to the number of transfers desired. The column address must be incremented after each transfer to prevent overwrites during the burst.
DRAM is typically refreshed at least once every 15.6 microseconds, the period between refreshes in a system being the refresh period. In the past, typical DRAM systems have had maximum transaction lengths which are only a small fraction of the refresh period. For example, a design employing an Intel i960.RTM. microcontroller has a maximum burst length of no more than four words. Thus, maximum transaction latency is so small as a percentage of the refresh period that a refresh rate can be set easily to accommodate a worse case scenario. As demand for increased throughput has grown, the burst length of various devices such as direct memory access (DMA) controllers have increased dramatically such that the above strategy is no longer viable on such high throughput systems. Taking, for example, a DRAM transaction in which a DMA bursts 512 words to a DRAM, such transaction could have a wait state profile of 7-3-3-3 . . . +4 RAS precharge states. Accordingly, even excluding master inserted wait states the transaction will require 1,544 cycles to complete. At 33 MHz, 1,544 cycles translate into 46.3 microseconds. As mentioned above, 46.3 microseconds is nearly three times the typical maximum time between refreshes. Some prior art systems have attempted to address this problem by forcing the master off the bus at regular intervals to allow a refresh to take place. Thus, large transactions are broken up into several smaller transactions. Many transactions are not well suited to be arbitrarily broken up based on a desired refresh rate. Moreover, breaking up the transaction increases overhead including bus arbitration, and any other overhead paid on a per transaction basis. Resource availability may also be an issue, e.g., where ownership of the resource must be obtained for the transaction to occur (writing to shared memory usually requires ownership of a synchronization object such as a mutex). Additionally, since the refresh is not transparent to the master, design of the master is more complicated.
Additionally, many prior art memory controllers are incapable of accommodating a "master not ready signal" which suspends the transaction without requiring the master to relinquish the bus. In such prior art systems, if the data was not available to be written at the expected time or the master was not prepared to read data at the appropriate time, invalid transactions resulted or the master was forced off the bus and required to come back later. One approach to handling the possibility of a master not ready is to introduce local buffering between the DRAM and the master. In this manner, the master can post DRAM writes to the buffers. Posted writes can then be written out to DRAM at leisure by the memory controller. This approach requires a large amount of logic and results in relatively high DRAM read latency. This approach is widely used in personal computer chip sets, but it is not suitable for use in pin constrained systems as it requires two complete interfaces one between the MCU memory and one between the local bus and the MCU.
Where pin constraints are an issue, the DRAM has typically been connected to the data lines of the local bus of the host processor. Connecting the DRAM directly to the data lines reduces the logic required as well as the latency of DRAM reads. However, as no buffering is provided, write posting is not possible. Since data automatically appears on the data lines from the DRAM in the case of a read, and, whatever is on the data lines during a write goes directly to memory, some accommodations must be made if the master needs to suspend the transaction. This required accommodation necessitates dynamic control of the memory controller's control signals.
In view of the foregoing, it is desirable to be able to provide a memory controller supporting a master not ready condition and mid-transaction refresh.